arion_arm Namespace Reference

Classes
class	ArchManagerARM
	A class responsible for performing architecture specific operations in case of an ARM chip emulation. More...

Variables
std::map< uint64_t, std::string >	NAME_BY_SYSCALL_NO
	A map identifying an ARM syscall name given its number.
std::map< std::string, arion::REG >	ARCH_REGS
	A map identifying a Unicorn ARM register given its name.
std::map< arion::REG, uint8_t >	ARCH_REGS_SZ
	A map identifying a Unicorn ARM register size given the register.
std::vector< arion::REG >	CTXT_REGS
	The list of high-level ARM registers that make up the context to be saved and restored.
std::map< uint64_t, arion::CPU_INTR >	IDT = {}
	The ARM Interrupt Descriptor Table.
arion::ABI_REGISTERS	ABI_REGS = arion::ABI_REGISTERS(UC_ARM_REG_PC, UC_ARM_REG_SP)
	Unicorn ARM PC and SP registers for genericity.
arion::ABI_CALLING_CONVENTION	ABI_CALLING_CONV
	Unicorn ARM registers involved in calling convention.
arion::ABI_SYSCALLING_CONVENTION	ABI_SYSCALLING_CONV
	Unicorn ARM registers involved in syscalling convention.
arion::KERNEL_SEG_FLAGS	SEG_FLAGS = ARION_ARM_TRAPS_PRESENT
	ARM flags telling the loader which kernel segments should be mapped in memory.
uint32_t	HWCAP2 = 0
	Some well working ARM chip HWCAP2 value.
uint32_t	HWCAP = 0x001fb8d7
	Some well working ARM chip HWCAP value.
const size_t	PTR_SZ = 4
	Size in bytes of a pointer in an ARM chip.
const uint16_t	ARCH_SZ = 32
	Size in bits of the ARM general-purpose registers.
arion::CPU_ARCH	ARCH = arion::CPU_ARCH::ARM_ARCH
	Arion CPU_ARCH for ARM.
arion::ARCH_ATTRIBUTES	ARCH_ATTRS
	Multiple architecture specific attributes for ARM, grouped in a structure for genericity purpose.

Variable Documentation

ABI_CALLING_CONV

arion::ABI_CALLING_CONVENTION arion_arm::ABI_CALLING_CONV

inline

Initial value:

=
    arion::ABI_CALLING_CONVENTION(UC_ARM_REG_R0, {UC_ARM_REG_R0, UC_ARM_REG_R1, UC_ARM_REG_R2, UC_ARM_REG_R3})

Unicorn ARM registers involved in calling convention.

ABI_REGS

arion::ABI_REGISTERS arion_arm::ABI_REGS = arion::ABI_REGISTERS(UC_ARM_REG_PC, UC_ARM_REG_SP)

inline

Unicorn ARM PC and SP registers for genericity.

ABI_SYSCALLING_CONV

arion::ABI_SYSCALLING_CONVENTION arion_arm::ABI_SYSCALLING_CONV

inline

Initial value:

= arion::ABI_SYSCALLING_CONVENTION(
    UC_ARM_REG_R7, UC_ARM_REG_R0,
    {UC_ARM_REG_R0, UC_ARM_REG_R1, UC_ARM_REG_R2, UC_ARM_REG_R3, UC_ARM_REG_R4, UC_ARM_REG_R5, UC_ARM_REG_R6})

Unicorn ARM registers involved in syscalling convention.

ARCH

arion::CPU_ARCH arion_arm::ARCH = arion::CPU_ARCH::ARM_ARCH

inline

Arion CPU_ARCH for ARM.

ARCH_ATTRS

arion::ARCH_ATTRIBUTES arion_arm::ARCH_ATTRS

inline

Initial value:

=
    arion::ARCH_ATTRIBUTES(ARCH, ARCH_SZ, PTR_SZ, HWCAP, HWCAP2, SEG_FLAGS, ABI_REGS, ABI_CALLING_CONV,
                           ABI_SYSCALLING_CONV, NAME_BY_SYSCALL_NO)

Multiple architecture specific attributes for ARM, grouped in a structure for genericity purpose.

ARCH_REGS

std::map<std::string, arion::REG> arion_arm::ARCH_REGS

inline

A map identifying a Unicorn ARM register given its name.

ARCH_REGS_SZ

std::map<arion::REG, uint8_t> arion_arm::ARCH_REGS_SZ

inline

A map identifying a Unicorn ARM register size given the register.

ARCH_SZ

const uint16_t arion_arm::ARCH_SZ = 32

inline

Size in bits of the ARM general-purpose registers.

CTXT_REGS

std::vector<arion::REG> arion_arm::CTXT_REGS

inline

Initial value:

= {
    UC_ARM_REG_R0,      UC_ARM_REG_R1,      UC_ARM_REG_R2,       UC_ARM_REG_R3,    UC_ARM_REG_R4,   UC_ARM_REG_R5,
    UC_ARM_REG_R6,      UC_ARM_REG_R7,      UC_ARM_REG_R8,       UC_ARM_REG_R9,    UC_ARM_REG_R10,  UC_ARM_REG_R11,
    UC_ARM_REG_R12,     UC_ARM_REG_SP,      UC_ARM_REG_LR,       UC_ARM_REG_PC,    UC_ARM_REG_SB,   UC_ARM_REG_SL,
    UC_ARM_REG_FP,      UC_ARM_REG_IP,      UC_ARM_REG_Q0,       UC_ARM_REG_Q1,    UC_ARM_REG_Q2,   UC_ARM_REG_Q3,
    UC_ARM_REG_Q4,      UC_ARM_REG_Q5,      UC_ARM_REG_Q6,       UC_ARM_REG_Q7,    UC_ARM_REG_Q8,   UC_ARM_REG_Q9,
    UC_ARM_REG_Q10,     UC_ARM_REG_Q11,     UC_ARM_REG_Q12,      UC_ARM_REG_Q13,   UC_ARM_REG_Q14,  UC_ARM_REG_Q15,
    UC_ARM_REG_CPSR,    UC_ARM_REG_APSR,    UC_ARM_REG_SPSR,     UC_ARM_REG_FPSCR, UC_ARM_REG_IPSR, UC_ARM_REG_CONTROL,
    UC_ARM_REG_PRIMASK, UC_ARM_REG_BASEPRI, UC_ARM_REG_FAULTMASK}

The list of high-level ARM registers that make up the context to be saved and restored.

HWCAP

uint32_t arion_arm::HWCAP = 0x001fb8d7

inline

Some well working ARM chip HWCAP value.

HWCAP2

uint32_t arion_arm::HWCAP2 = 0

inline

Some well working ARM chip HWCAP2 value.

IDT

std::map<uint64_t, arion::CPU_INTR> arion_arm::IDT = {}

inline

The ARM Interrupt Descriptor Table.

NAME_BY_SYSCALL_NO

std::map<uint64_t, std::string> arion_arm::NAME_BY_SYSCALL_NO

inline

A map identifying an ARM syscall name given its number.

PTR_SZ

const size_t arion_arm::PTR_SZ = 4

inline

Size in bytes of a pointer in an ARM chip.

SEG_FLAGS

arion::KERNEL_SEG_FLAGS arion_arm::SEG_FLAGS = ARION_ARM_TRAPS_PRESENT

inline

ARM flags telling the loader which kernel segments should be mapped in memory.